A Parallel Genetic Algorithm for Multiobjective Microprocessor Design

The microprocessor chip designer must solve the problem of partitioning millions of transistors into an arbitrary number of hardware structures within a nite chip area toward achieving maximumperformance. This combinative complexity is compounded by a lengthy performance evaluation of each proposed design. We present the application of a real-valued multiobjective genetic algorithm on an asynchronous parallel workstation network as a optimization approach well suited to this problem. By casting design budget constraints as multiple design objectives, the need for penalty functions is eliminated. A microprocessor cache memory design problem is optimized with the genetic algorithm. Microprocessor chip designers now have more transistors and design alternatives available to them than at any time in the past. The chip designer's selection of hardware structures from many alternatives (e.g., adders, multipliers, memories) must maximize microprocessor performance. The designer must solve the combinatorial design problem of partitioning millions of transistors into an arbitrary number of hardware structures within a nite chip area while achieving this goal. At the most basic level the microprocessor design problem is characterized by: 1. specifying nite chip size and power dissipation budget constraints, 2. specifying chip performance objectives, 3. selecting and interconnecting many hardware structures, each of which consumes area from a real-estate budget, and power from a power budget , into a chip microarchitecture, 4. organizing these structures to provide maximum performance within all design budgets, 5. modeling the microarchitecture in a high-level language and simulating its performance, 6. proposing modiications to the speciications and microarchitecture to overcome quantiied performance shortcomings, 7. iterating this process until a balanced, near-optimal design is identiied. Performance interactions exist between interconnected hardware structures. Each microarchitectural design iteration alters these interactions, and requires an entire re-assessment of the utility of each hardware structure in the context of the new design. Questions regarding whether the hardware is best spent between multiple competing structures must be constantly re-evaluated, e.g., increasing the size of some on-chip hardware structure M means that less hardware is available for on-chip hardware structures N, O, and P. The similarity between the microarchitectural design problem and NP-complete problems such as set partitioning or bin packing is apparent. The combinative complexity faced by the designer is exacerbated by the computationally expensive performance evaluation of a proposed design. As technology improvements provide more transistors and chip area for design use, this complexity continues to grow. Ironically, the business climate demands increasingly shorter design …